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n01l1618n1a (doc# 14-02-009 rev g ecn# 01-0995) 1 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. ami semiconductor, inc. ulp memory solutions 670 north mccarthy blvd. suite 220 milpitas, ca 95035 ph: 408-935-7777, fax: 408-935-7770 1mb ultra-low power asynchronous cmos sram 64k 16 bit overview the n01l1618n1a is an integrated memory device containing a 1 mbit static random access memory organized as 65,536 words by 16 bits. the device is designed and fabricated using ami semiconductor?s advanced cmos technology to provide both high-speed performance and ultra-low power. the device operates with a single chip enable (ce ) control and output enable (oe ) to allow for easy memory expansion. byte controls (ub and lb ) allow the upper and lower bytes to be accessed independently. the n01l1618n1a is optimal for various applicat ions where low-power is critical such as battery backup and hand-held devices. the device can op erate over a very wide temperature range of -40 o c to +85 o c and is available in jedec standard packages compatible with other standard 64kb x 16 srams. features ? single wide power supply range 1.65 to 2.2 volts ? very low standby current 0.5a at 1.8v (typical) ? very low operating current 0.7ma at 1.8v and 1s (typical) ? very low page mode operating current 0.5ma at 1.8v and 1s (typical) ? simple memory control single chip enable (ce ) byte control for independent byte operation output enable (oe ) for memory expansion ? low voltage data retention vcc = 1.2v ? very fast output enable access time 30ns oe access time ? automatic power down to standby mode ? ttl compatible three-state output driver ? compact space saving bga package avail- able ? rohs compliant product family part number package type operating temperature power supply (vcc) speed standby current (i sb ), typical operating current (icc), typical n01l1618n1ab 48 - bga -40 o c to +85 o c 1.65v - 2.2v 70ns @ 1.8v 85ns @ 1.65v 0.5 a 0.7 ma @ 1mhz n01l1618n1at 44 - tsop ii n01l1618n1ab2 48 - bga green n01l1618n1at2 44 - tsop ii green
(doc# 14-02-009 rev g ecn# 01-0995) 2 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. pin configurations pin descriptions pin name pin function a 0 -a 15 address inputs we write enable input ce chip enable input oe output enable input lb lower byte enable input ub upper byte enable input i/o 0 -i/o 15 data inputs/outputs nc not connected v cc power v ss ground pin one 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a 4 a 3 a 2 a 1 a 0 ce i/o 0 i/o 1 i/o 2 i/o 3 vcc vss i/o 4 i/o 5 i/o 6 i/o 7 we a 15 a 14 a 13 a 12 nc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a 5 a 6 a 7 oe ub lb i/o 15 i/o 14 i/o 13 i/o 12 vss vcc i/o 11 i/o 10 i/o 9 i/o 8 nc a 8 a 9 a 10 a 11 nc n01l1618n1a tsop 123456 a lb oe a 0 a 1 a 2 nc b i/o 8 ub a 3 a 4 ce i/o 0 c i/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 d v ss i/o 11 nc a 7 i/o 3 v cc e v cc i/o 12 nc nc i/o 4 v ss f i/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 g i/o 15 nc a 12 a 13 we i/o 7 h nc a 8 a 9 a 10 a 11 nc 48 pin bga (top) 6 x 8 mm
(doc# 14-02-009 rev g ecn# 01-0995) 3 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. functional block diagram functional description ce we oe ub lb i/o 0 - i/o 15 1 1. when ub and lb are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb only is in the select mode only i/o 0 - i/o 7 are affected as shown. when ub is in the select mode only i/o 8 - i/o 15 are affected as shown. mode power hxxxx high z standby 2 2. when the device is in standby mode, control inputs (we , oe , ub , and lb ), address inputs and data input/outputs are internally isolated from any external in fluence and disabled from exerti ng any influence externally. standby l x x h h high z active active ll x 3 3. when we is invoked, the oe input is internally disabled and has no effect on the circuit. l 1 l 1 data in write 3 active -> standby 4 lhl l 1 l 1 data out read active -> standby 4 lhh l 1 l 1 high z active standby 4 4. the device will consume active power in this mode whenever addresses are changed. data inputs are internally isolated from an y external influence. capacitance 1 1. these parameters are verified in device characterization and are not 100% tested item symbol test condition min max unit input capacitance c in v in = 0v, f = 1 mhz, t a = 25 o c 8pf i/o capacitance c i/o v in = 0v, f = 1 mhz, t a = 25 o c 8pf address inputs a0 - a3 address inputs a4 - a15 word address decode logic 4k page x 16 word x 16 bit ram array word mux input/ output mux and buffers page address decode logic control logic ce we oe ub lb i/o0 - i/o7 i/o8 - i/o15
(doc# 14-02-009 rev g ecn# 01-0995) 4 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. absolute maximum ratings 1 1. stresses greater than those listed above may cause permanent da mage to the device. this is a stress rating only and functiona l operation of the device at these or any ot her conditions above thos e indicated in the operating se ction of this specification i s not implied. exposure to absolute maximum rating condi tions for extended periods may affect reliability. item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 3.0 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 o c operating temperature t a -40 to +85 o c soldering temperature and time t solder 260 o c, 10sec o c operating characteristics (ove r specified temperature range) item symbol test conditions min. typ 1 1. typical values are measured at vcc=vcc typ., t a =25c and are not 100% tested. max unit supply voltage v cc 1.65 1.8 2.2 v data retention voltage v dr chip disabled 3 1.2 v input high voltage v ih 0.7v cc v cc +0.3 v input low voltage v il ?0.3 0.3v cc v output high voltage v oh i oh = 0.2ma v cc ?0.3 v output low voltage v ol i ol = -0.2ma 0.3 v input leakage current i li v in = 0 to v cc 0.5 a output leakage current i lo oe = v ih or chip disabled 0.5 a read/write operating supply current @ 1 s cycle time 2 2. this parameter is specified with the ou tputs disabled to avoid external loading ef fects. the user must add current required t o drive output capacitance expected in the actual system. i cc1 v cc =2.2 v, v in =v ih or v il chip enabled, i out = 0 0.7 3.0 ma read/write operating supply current @ 85 ns cycle time 2 i cc2 v cc =2.2 v, v in =v ih or v il chip enabled, i out = 0 816ma page mode operating supply current @ 85ns cycle time 2 (refer to power savings with page mode operation diagram) i cc3 v cc =2.2 v, v in =v ih or v il chip enabled, i out = 0, 3 ma read/write quiescent operating sup- ply current 3 3. this device assumes a standby m ode if the chip is disabled (ce high). in order to achieve low standby current all inputs must be within 0.2 volts of either vcc or vss i cc4 v cc =2.2 v, v in =v ih or v il chip enabled, i out = 0, f = 0 20 a maximum standby current 3 i sb1 v in = v cc or 0v chip disabled t a = 85 o c, v cc = 2.2 v 0.5 10 a maximum data retention current 3 i dr v cc = 1.2v, v in = v cc or 0 chip disabled, t a = 85 o c 5 a
(doc# 14-02-009 rev g ecn# 01-0995) 5 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. power savings with page mode operation (we = v ih ) note: page mode operation is a method of addressing the sram to save operating current. the internal organization of the sram is optimized to allow this unique operating mode to be used as a valuable power saving feature. the only thing that needs to be done is to address the sram in a manner that the internal page is left open and 16-bit words of data are read from the open page. by treating addresses a0-a3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power srams. page address (a4 - a15 ) lb , ub oe ce word address (a0 - a3) open page word 1 word 2 word 16 ...
(doc# 14-02-009 rev g ecn# 01-0995) 6 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. timing test conditions item input pulse level 0.1v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc output load cl = 30pf operating temperature -40 to +85 o c timing item symbol 1.65 - 2.2 v 1.8 - 2.2 v units min. max. min. max. read cycle time t rc 85 70 ns address access time t aa 85 70 ns chip enable to valid output t co 85 70 ns output enable to valid output t oe 35 30 ns byte select to valid output t lb , t ub 30 25 ns chip enable to low-z output t lz 10 10 ns output enable to low-z output t olz 55ns byte select to low-z output t lbz , t ubz 10 10 ns chip disable to high-z output t hz 30 25 ns output disable to high-z output t ohz 30 25 ns byte select disable to high-z output t lbhz , t ubhz 30 25 ns output hold from address change t oh 55ns write cycle time t wc 85 70 ns chip enable to end of write t cw 50 40 ns address valid to end of write t aw 50 40 ns byte select to end of write t lbw , t ubw 50 40 ns write pulse width t wp 50 40 ns address setup time t as 00ns write recovery time t wr 00ns write to high-z output t whz 25 20 ns data to write time overlap t dw 40 35 ns data hold from write time t dh 00 ns end write to low-z output t ow 10 10 ns
(doc# 14-02-009 rev g ecn# 01-0995) 7 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. timing of read cycle (ce = oe = v il , we = v ih ) timing waveform of read cycle (we = v ih ) address data out t rc t aa t oh data valid previous data valid address lb , ub oe data valid t rc t aa t co t hz t ohz t lbhz, t ubhz t olz t oe t lz high-z data out t lb, t ub t lblz, t ublz ce
(doc# 14-02-009 rev g ecn# 01-0995) 8 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. timing waveform of write cycle (we control) timing waveform of write cycle (ce control) address data in ce lb , ub data valid t wc t aw t cw t wr t whz t dh high-z we data out high-z t ow t as t wp t dw t lbw , t ubw address we data valid t wc t aw t cw t wr t dh ub , lb data in high-z t as t wp t lz t dw t lbw , t ubw data out t whz ce
(doc# 14-02-009 rev g ecn# 01-0995) 9 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. 44-lead tsop ii package (t44) note: 1. all dimensions in millimeters 2. package dimensions exclude molding flash 18.410.13 10.160.13 see detail b 1.100.15 11.760.20 0.45 0.30 0.80mm ref detail b 0.80mm ref 0 o -8 o 0.20 0.00
(doc# 14-02-009 rev g ecn# 01-0995) 10 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. ball grid array package dimensions (mm) de e = 0.75 ball matrix type sd se j k 60.10 80.10 0.375 0.375 1.125 1.375 full side view top view bottom view e d a1 ball pad corner (3) 1.240.10 0.280.05 0.15 0.05 z z 1. 0.350.05 dia. 1. dimension is measured at the maximum solder ball diameter. parallel to primary z. 2. primary datum z and seating plane are defined by the spherical crowns of the solder balls. 3. a1 ball pad corner i.d. to be marked by ink. 2. seating plane - z sd se e k typ j typ e a1 ball pad corner
(doc# 14-02-009 rev g ecn# 01-0995) 11 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. n01l1618n1a ami semiconductor, inc. ordering information ? 2006 ami semiconductor, inc. all rights reserved. ami semiconductor, inc. ("amis") reserves the right to change or modify the information contained in this data sheet and the pr oducts described therein, without prior notice. amis does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. amis makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does amis assume an y liability arising out of t he application or use of any product or circuit described herein. amis does not authorize use of its products as critical components in any application in which the failure of the amis product may be expected to result in significant injury or death, incl uding life support systems and critical medical instruments. revision history revision # date change description a jan. 2001 initial advance release b apr. 2001 changed operating voltage to 2.2v. other minor erratas. c dec. 2001 part number change from em064u16, modi fied overview and features, added page mode operation diagam, revised o perating characteristics table, func- tional description table and ordering information diagram d nov. 2002 replaced isb and icc on product family table with typical values e oct. 2004 added pb-free and green package option f nov. 2005 removed pb-free pkg, added greenn pkg & rohs compliant g september 2006 converted to ami semiconductor n01l1618n1ax -xx x i = industrial, -40c to 85c 70 = 70ns t = 44-pin tsop ii b = 48-ball bga t2 = 44-pin tsopii green package (rohs compliant) b2 = 48-ball bga green package (rohs compliant) temperature performance package type

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